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publication number S25FL204K_00 revision 05 issue date august 14, 2012 S25FL204K S25FL204K cover sheet 4-mbit 3.0v serial flash memory with uniform 4 kb sectors data sheet (preliminary) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product described herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) notice on data sheet designations spansion inc. issues data sheets with advance informat ion or preliminary designati ons to advise readers of product information or intended s pecifications throughout the produc t life cycle, including development, qualification, initial production, and full production. in all cases, however, reader s are encouraged to verify that they have the latest information before finalizi ng their design. the following descriptions of spansion data sheet designations are presented here to hi ghlight their presenc e and definitions. advance information the advance information designation i ndicates that spansion inc. is de veloping one or more specific products, but has not committed any des ign to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore plac es the following conditions upo n advance information content: ?this document contains information on one or more products under development at spansion inc. the information is intended to help you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the product development has pr ogressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these aspects of production under c onsideration. spansion places the following conditi ons upon preliminary content: ?this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designati ons (advance information, preliminary, or full production). th is type of document distinguishes t hese products and their designations wherever necessary, typically on the first page, th e ordering information page, and pages with the dc characteristics table and the ac er ase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of ti me such that no changes or only nominal changes are expected, the preliminary desi gnation is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the a ddition or deletion of a speed option, temperat ure range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographic al error or incorrect specificati on. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these document designations may be directed to your local sales office.
this document states the current technical specifications rega rding the spansion product(s) described herein. the preliminary s tatus of this document indicates that product qual- ification has been completed, and that initial production has begu n. due to the phases of the manufacturing process that requir e maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. publication number S25FL204K_00 revision 05 issue date august 14, 2012 distinctive features ? single power supply operation ? full voltage range: 2.7 to 3.6v ? 4-mbit serial flash ? 4-mbit/512 kbyte/2048 pages ? 256 bytes per programmable page ? uniform 4-kbyte sectors/64-kbyte blocks ? standard and dual ? standard spi: sck, cs#, si, so, wp#, hold# ? dual spi: sck, cs#, si/io0, so, wp#, hold# ? fast read dual output instruction ? auto-increment read capability ? high performance ? fast read (serial): 85 mhz clock rate ? dual output read: 85 mhz clock rate ? low power consumption ? 12 ma typical active current ? 15 a typical standby current ? flexible architecture with 4 kb sectors ? sector erase (4 kb) ? block erase (64 kb) ? page program up to 256 bytes ? 100k erase/program cycles typical ? 20-year data retention typical ? software and hardware write protection ? write protect all or portion of memory via software ? enable/disable protection with wp# pin ? high performance program/erase speed ? page program time: 1.5 ms typical ? sector erase time (4 kb): 50 ms typical ? block erase time (64 kb): 500 ms typical ? chip erase time: 3.5 seconds typical ? package options ? 8-pin soic 150/208-mil ? all pb-free packages are rohs compliant general description the S25FL204K (4-mbit, 512-kbyte) serial flash memory, wi th advanced write protection mechanisms. theS25FL204K supports the standard serial pe ripheral interface (spi), and a high performance dual out put using spi pins: serial clock, chip select, serial si/io0, so, wp# and hold#. spi clock frequencies of up to 85 mhz are supported along with a clock rate of 85 mhz for dual output read. the S25FL204K array is organized into 2048 programmable pages of 256 bytes each. up to 256 bytes can be programmed at a time. pages can be erased in groups of 16 (4 kb sector eras e), groups of 256 (64 kb block er ase) or the entire chip (chip erase). the S25FL204K has128 erasable sector s and 8 erasable blocks. the small 4 kb se ctors allow for greater flexibility in applications that require data and parameter storage. a hold pin, write protect pin and programm able write protection provide further cont rol flexibility. additionally, the s25fl204 k device supports jedec standard manufacturer and device identification. S25FL204K 4-mbit 3.0v serial flash memory with uniform 4 kb sectors data sheet (preliminary)
4 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) table of contents distinctive features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2. connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5. memory organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.1 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2 dual output spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.3 hold function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.4 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7. write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1 page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 sector erase, block erase, and chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 polling during a write, program, or erase cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4 active power, stand-by power, and deep power-down modes . . . . . . . . . . . . . . . . . . . . . . 14 8. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 write enable (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.2 write disable (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.3 read status register (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.4 write status register (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.5 read data (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.6 fast read (0bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.7 fast read dual output (3bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.8 page program (pp) (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.9 sector erase (se) (20h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.10 block erase (be) (d8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.11 chip erase (ce) (c7h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.12 deep power-down (dp) (b9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.13 release deep power-down / device id (abh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.14 read manufacturer / device id (90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.15 read identification (rdi d) (9fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.1 power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.3 recommended operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.5 ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10. package material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.1 8-pin soic 150-mil package (soa 008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.2 8-pin soic 208-mil package (soc 008). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
august 14, 2012 S25FL204K_00_05 S25FL204K 5 data sheet (preliminary) figures figure 2.1 8-pin soic (150/208 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5.1 memory organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6.1 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6.2 hold condition waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8.1 write enable command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8.2 write disable command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8.3 read status register command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8.4 write status r egister command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8.5 read data command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8.6 fast read command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8.7 fast read dual output command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8.8 page program command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 figure 8.9 sector erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8.10 block erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8.11 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8.12 deep power-down command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8.13 release deep power-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 figure 8.14 release deep power-down / device id command sequence . . . . . . . . . . . . . . . . . . . . . . . 25 figure 8.15 read manufacturer / device id command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8.16 read jedec id command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9.1 power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9.2 ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 9.3 serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9.4 input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9.5 hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) tables table 3.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 4.1 S25FL204K valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 6.1 status register bit locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 7.1 protected area sizes bl ock organization ? S25FL204K . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 8.1 command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 8.2 manufacturer and device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 9.1 power-up voltage and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 9.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 9.3 recommended operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9.4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 9.5 ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 9.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
august 14, 2012 S25FL204K_00_05 S25FL204K 7 data sheet (preliminary) 1. block diagram 2. connection diagrams addre ss b u ffer s a nd l a tche s x-decoder fl as h memory y-decoder control logic i/o b u ffer s a nd d a t a l a tche s s eri a l interf a ce c s # s ck s i/io0 s owp#hold# 1 2 3 4 c s # s o wp# gnd s i/io0 s ck hold# vcc 5 6 7 8 figure 2.1 8-pin soic (150/208 mil)
8 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) 3. signal descriptions serial data input / output (si/io0) the spi serial data input/output (s i/io0) pin provides a means for in structions, addresses and data to be serially written to (shifted into) the device. data is latched on the rising edge of t he serial clock (sck) input pin. the si/io0 pin is also used as an output pin when the fast read dual outp ut instruction is executed. serial data output (so) the spi serial data output (so) pin provides a means fo r data and status to be seri ally read from (shifted out of) the device. data is shift ed out on the falling edge of the serial clock (sck) input pin. serial clock (sck) the spi serial clock input (sck) pin provides the timing for seri al input and output operations. see spi modes on page 11. chip select (cs#) the spi chip select (cs#) pin enables and disables de vice operation. when cs# is high the device is deselected and the serial data ou tput pins are at high impedance. when deselected, the device?s power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. when cs# is brought low the device will be selected, power consumption will increase to active levels and instru ctions can be written to and data read from the device. after power-up, cs# must transition from high to low before a new instru ction will be accepted. hold (hold#) the hold# pin allows the device to be paused while it is actively selected. when hold# is brought low, while cs# is low, the so pin will be at high im pedance and signals on the si and sck pins will be ignored (don?t care). the hold# function ca n be useful when multiple devices are sharing the same spi signals. write protect (wp#) the write protect (wp#) pin can be used to prevent th e status register from being written. used in conjunction with the status regist er?s block protect (bp0, bp1 and bp2, bp3) bits and status register protect (srp) bits, a portion or the entire memory array can be hardware protected. note: 1. si/io0 output is used for dual output read instruction. table 3.1 pin descriptions symbol pin name sck serial clock input si/io0 serial data input / output (1) so serial data output cs# chip enable wp# write protect hold# hold input vcc supply voltage (2.7-3.6v) gnd ground
august 14, 2012 S25FL204K_00_05 S25FL204K 9 data sheet (preliminary) 4. ordering information the ordering part number is formed by a valid combination of the following: 4.1 valid combinations table 4.1 lists the valid combinations co nfigurations planned to be support ed in volume for this device. s25fl 204 k 0t m f i 01 1 packing type 0 = tray 1 = tube 3 = 13? tape and reel model number (additional ordering options) 04 = 8-pin so package (150 mil) 01 = 8-pin so package (208 mil) temperature range i = industrial (?40c to +85c) package materials f = lead (pb)-free package type m = 8-pin so package speed 0t = 85 mhz device technology k = 0.09 m process technology density 204 = 4 mbit device family s25fl spansion memory 3.0 volt-only, serial peripheral interface (spi) flash memory table 4.1 S25FL204K valid combinations S25FL204K valid combinations package marking base ordering part number speed option package and temperature model number packing type S25FL204K 0t mfi 01, 04 0, 1, 3 fl204kif
10 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) 5. memory organizations the memory is organized as: ? 524,288 bytes ? uniform sector architecture ? 8 blocks of 64 kb ? 128 sectors of 4 kb ? 2,048 pages (256 bytes each) each page can be individually programmed (bits are programm ed from 1 to 0). the devi ce is sector, block or chip erasable but not page erasable. figure 5.1 memory organization xxff00h xxffffh .. xxf000h xxf0ffh xxef00h xxefffh .. xxe000h xxe0ffh 07ff00h 07ffffh .. 070000h 0700ffh 06ff00h 06ffffh .. 060000h 0600ffh xx1f00h xx1fffh .. xx1000h xx10ffh xx0f00h xx0fffh 00ff00h 00ffffh .... xx0000h xx00ffh 000000h 0000ffh ? ... s ector 15 (4 kb) s ector 14 (4 kb) s ector 0 (4 kb) s ector 1 (4 kb) block 6 (64 kb) block 7 (64 kb) block 0 (64 kb)
august 14, 2012 S25FL204K_00_05 S25FL204K 11 data sheet (preliminary) 6. functional description 6.1 spi modes the S25FL204K device can be driven by an embedded mi crocontroller (bus master ) in either of the two following clocking modes. ? mode 0 with clock polarity (cpol) = 0 and, clock phase (cpha) = 0 ? mode 3 with cpol = 1 and, cpha = 1 for these two modes, input data into the device is al ways latched in on the rising edge of the sck signal and the output data is always availabl e from the falling edge of the sck cloc k signal. the diff erence between the two modes is the clock polarity w hen the bus master is in standby mode and not transferring any data. ? sck will stay at logic low state with cpol = 0, cpha = 0 ? sck will stay at logic high st ate with cpol = 1, cpha = 1 figure 6.1 spi modes 6.2 dual output spi the S25FL204K supports dual output operation when using the ?fast read with dual output? (3b hex) command. this feature allows data to be transferred from the serial flash at twice the rate possible with the standard spi. this command can be used to quickly download code from flash to ram upon power-up (code-shadowing) or for applic ations that cache code-segm ents to ram for execution. the dual output feature simply allo ws the spi data input pin (si) to also serve as an output during this command. all other operations use the standard spi interface with single signal. the host keeps cs# low and hold# high. the write protect (wp#) signal is ignor ed. the memory drives data on the si/io0 and so signals during the dual output cycles. the next interf ace state continues to be dual output cycle until the host returns cs# to high ending the command. 6.3 hold function the hold (hold#) signal is used to pause any seri al communications with t he S25FL204K device without deselecting the device or stopping the serial clock. to enter the hold c ondition, the device must be selected by driving the cs# input to the logi c low state. it is recommended that the user keep the cs# input low state during the entire duration of t he hold condition. this is to ensure that the state of the interface logic remains unchanged from the moment of entering the hold condition. if the cs# input is driv en to the logic high state while the device is in the hold condition, the inte rface logic of the device will be reset. to restart communication with the device, it is necessary to driv e hold# to the logic high state while driving the cs# signal into the logic low state. this prevents the device from going back into the hold condition. the hold condition starts on the fal ling edge of the hold (hold#) signal, provided that this coincides with sck being at the logic low st ate. if the falling edge does not coinci de with the sck signal being at the logic low state, the hold condition starts whenever the sck signal reaches t he logic low state. taking the hold# cs# mode3 mode 0 mode 3 si/io0 dont care so bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 msb msb high impedance sck mode0
12 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) signal to the logic low stat e does not terminate any writ e, program or erase operat ion that is currently in progress. during the hold condition, so is in high impedance and both the si and sck input are don't care. the hold condition ends on the rising edge of the hold (hold#) signa l, provided that this co incides with the sck signal being at the logic low state. if the rising edge does not coincide with the sck signal being at the logic low state, the hold condition ends whenever the sck signal reaches the logic low state. figure 6.2 hold condition waveform 6.4 status register the status register c ontains a number of status and control bits th at can be read or set (as appropriate) by specific instructions ? write in progress (wip) is a read only bit in the stat us register (r0) which indi cates whether the device is performing a program, write, erase operation, or any other operation, during which a new operation command will be ignored. when the wip bit is set to 1, the device is busy performing an operation. when the bit is cleared to 0, no operation is in progress. ? write enable latch (wel) is a read only bit in the st atus register (r1) that must be set to 1 to enable program, write, or erase operations as a means to provide protection against inadvertent changes to memory or register values. the wr ite enable (wren) command executi on sets the write enable latch to a 1 to allow any program, erase, or write commands to execute afterwards. the write disable (wrdi) command can be used to set the write enable latch to a 0 to prevent all program, erase, and write commands from execution. the wel bit is cleared to 0 at the end of any successf ul program, write, or erase operation. after a power down/power up sequenc e, hardware reset, or software reset, the write enable latch is set to a 0. ? block protect bits (bp3, bp2, bp1, bp0) are non-volatile read/write bits in the status register (r5, r4, r3, and r2) that define the main fl ash array area to be software protected against program and erase commands. when one or more of the bp bits is set to 1, the relevant memory area is protected against program and erase. the chip erase (ce) command c an be executed only when the bp bits are cleared to 0?s. see table 7.1 on page 13 for a description of how the bp bit values select the memory array area protected. the factory defaul t setting for all the bp bits is 0, which implies that none of array is protected. ? reserved bits (rev) , status register bit location r6 is reserved for future use. current devices will read 0 for this bit location. it is recommended to mask out t he reserved bit when testing the status register. doing this will ensure compatib ility with future devices. ? the status register protect (srp) bit is a non-volatile read/write bit in status register (r7) that can be used in conjunction with the write protect (wp#) pin to disable writes to status register. when the srp bit is set to a 0 state (factory default) the wp# pin has no control over status regist er. when the srp pin is set sck hold# active hold active hold active table 6.1 status register bit locations r7 r6 r5 r4 r3 r2 r1 r0 srp rev bp3 bp2 bp1 bp0 wel wip
august 14, 2012 S25FL204K_00_05 S25FL204K 13 data sheet (preliminary) to a 1, the write status register instruction is locke d out while the wp# pin is low. when the wp# pin is high the write status regist er instruction is allowed. 7. write protection some basic protection agains t unintended changes to stor ed data is provided and controlled purely by the hardware design. these protection mechanisms in the S25FL204K device are described below: ? power-on reset and an internal timer (t puw ) can provide protection against inadvertent changes while the power supply is outside the operating specification. ? program, erase and write status regist er instructions are checked that th ey consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. ? all instructions that modify data must be preceded by a write enable (wren) inst ruction to set the write enable latch (wel) bit. this bit is retur ned to its reset state by the following events: ?power-up ? write disable (wrdi) instru ction completion or write status regist er (wrsr) instruction completion or page program (pp) instruction completion or sector erase (se) instruction completion or block erase (be) instruction completion or chip erase (ce) instruction completion ? the block protect (bp3, bp2, bp1, and bp0) bits allow part of the memory to be configured as read-only. this is the software protected mode (spm). ? the write protect (wp#) signal allows the block prot ect (bp3, bp2, bp1, bp0) bits and status register protect (srp) bit to be protected. this is the hardware protected mode (hpm). ? in addition to the low power consumption feature, the deep power-down mode offers extra software protection from inadver tent write, program and erase instructions , as all instructions are ignored except one particular instructi on (the release from deep po wer-down instruction). table 7.1 protected area sizes block organization ? S25FL204K status bit protect blocks bp3bp2bp1bp0 0000 0 (none) 0001 1 (1 block, block 7th) 0010 2 (2 blocks, block 6th~7th) 0011 3 (4 blocks, block 4th~7th) 0100 4 (8 blocks, all) 0101 5 (8 blocks, all) 0110 6 (8 blocks, all) 0111 7 (8 blocks, all) 1000 8 none 1001 9 ( 126 sectors, sector 0th~125th) 1010 10 ( 124 sectors, sector 0th~123rd) 1011 11 (120 sectors, sector 0th~ 119th) 1100 12 (112 sectors, sector 0th~ 111th) 1101 13 (96 sectors, sectors 0th~95th) 1110 14 (64 sectors, sectors 0th~63rd) 1111 15 (128 sectors, all)
14 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) 7.1 page programming to program one data byte, two inst ructions are required: write enabl e (wren), which is one byte, and a page program (pp) sequence, which consis ts of four bytes plus data. this is followed by the internal program cycle (of duration t pp ). to spread this overhead, the page program (pp) instructio n allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), pr ovided that they lie in consecutive addresses on the same page of memory. 7.2 sector erase, block erase, and chip erase the page program (pp) instruct ion allows bits to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be achieved a sector at a time, using the sector erase (se) instruction, a block at a time using the block erase (be) instruction or th roughout the entire memory, using the chip erase (ce) instruction. th is starts an internal er ase cycle (of duration t se, t be, or t ce ). the erase instruction must be preceded by a write enable (wren) instruction. 7.3 polling during a write, program, or erase cycle a further improvement in the time to write status register (wrsr), prog ram (pp) or erase (se, be, or ce) can be achieved by not waiting for the worst case delay (t w , t pp , t se , t be , or t ce ). the write in progress (wip) bit is provided in the status register so that the appl ication program can monitor its value, polling it to establish when the previous write cycle, program cycle or erase cycle is complete. 7.4 active power, stand-by power, and deep power-down modes when chip select (cs#) is low, the device is enabled, and in the active power mode. when chip select (cs#) is high, the device is disabled, but could remain in the active power mode until all internal cycles have completed (program, erase, write st atus register). the device then goe s into the standby power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when the spec ific instruction (the enter deep power-down mode (dp) instruction) is executed with the device consumption at i cc2 . the device remains in this mode until another specific instru ction (the release from deep power-down mode and read device id (rdi) instruction) is executed. all other instructions are ignored while the device is in the deep power-down mode. this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, progra m or erase instructions. 8. commands the command set of the S25FL204K consists of fifteen ba sic instructions that are fully controlled through the spi bus (see table 8.1 ). the host system must shift all commands , addresses, and data in and out of the device, beginning with the most significant bit. on the first rising edge of sck after cs# is driven low, the device accepts the one-byte command on si (all commands are one byte long), most significant bit first. each successive bit is latched on the rising edge of sck. every command sequence begins with a one-byte command code. the command may be followed by address, data, both, or nothing, depending on the command. cs# must be driven high after the last bit of the command sequence has been written. all commands that write, program or erase require that cs# be driven high at a byte boundary, otherwise the command is not ex ecuted. since a byte is co mposed of eight bits, cs# must therefore be driven high when the number of clock pulses after cs# is driven low is an exact multiple of eight. the device ignores any attempt to access the me mory array during a write registers, program, or erase operation, and continues the operation uninterrupted.
august 14, 2012 S25FL204K_00_05 S25FL204K 15 data sheet (preliminary) notes: 1. data bytes are shifted with most significant bit first. byte fields with data in parenthesis ?( )? indicate data being read f rom the device on the so pin. 2. the status register contents will repeat continuously until cs# te rminates the instruction. 3. see table 8.2, manufacturer and device identification on page 15 for device id information. 4. the device id will repeat continuously until cs# terminates the instruction. 8.1 write enable (06h) the write enable command ( figure 8.1 ) sets the write enable latch (wel) bi t in the status register to a 1, which enables the device to accept a write status register, progr am, or erase command. the wel bit must be set prior to every page program, sector erase, block eras e, chip erase, and write status register command. the host system must first drive cs# low, write the wren command, and then drive cs# high. table 8.1 command set command name byte1 code byte2 byte3 byte4 byte5 byte6 n-bytes write enable 06h write disable 04h read status register 05h (s7-s0) (1) (note 2) write status register 01h s7-s0 read data 03h a23-a16 a15-a8 a7-a0 (d7-d0) (next byte) continuous fast read 0bh a23-a16 a15-a8 a7-a0 dummy (d7-d0) (next byte) continuous fast read dual output 3bh a23-a16 a15-a8 a7-a0 dummy i/o= (d6, d4, d2, d0) o= (d7, d5, d3, d1) (one byte per 4 clocks, continuous) page program 02h a23-a16 a15-a8 a7-a0 (d7-d0) (next byte) up to 256 bytes block erase (64 kb) d8h a23-a16 a15-a8 a7-a0 sector erase (4 kb) 20h a23-a16 a15-a8 a7-a0 chip erase c7h/60h power-down b9h release power-down / device id abh dummy dummy dummy (id7-id0) (4) manufacturer / device id (3) 90h dummy dummy 00h (m7-m0) (id7-id0) jedec id 9fh (m7-m0) manufacturer (id15-id8) memory type (id7-id0) capacity table 8.2 manufacturer and devi ce identification op code (m7-m0) (id15-id0) (id7-id0) abh 12h 90h 01h 12h 9fh 01h 4013h
16 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) figure 8.1 write enable command sequence 8.2 write disable (04h) the write disable command ( figure 8.2 ) resets the write enable latch (wel) bit to a 0, which disables the device from accepting a writ e, program or erase comm and. the host system must first drive cs# low, write the wrdi command, and then drive cs# high. the wel bi t is automatically reset after power-up and upon completion of the write st atus register, page program, sector erase, block erase, and chip erase commands. figure 8.2 write disable command sequence 8.3 read status register (05h) the read status register (rdsr) command outputs the state of th e status register bits. the rdsr command may be written at any time, even while a prog ram, erase, or write registers operation is in progress. the host system should c heck the write in progres s (wip) bit before sending a new command to the device if an operation is already in progress. figure 8.3 shows the rdsr command sequence, which also shows that it is possible to read the status re gister continuously until cs# is driven high. (see section 6.4, status register on page 12 ). cs sck 05 4 3 1 2 7 6 mode0 mode0 mode3 mode3 si/io0 so high impedance instruction(06h) cs sck 05 4 3 1 2 7 6 mode0 mode0 mode3 mode3 si/io0 so high impedance instruction(04h)
august 14, 2012 S25FL204K_00_05 S25FL204K 17 data sheet (preliminary) figure 8.3 read status register command sequence 8.4 write status register (01h) the write status register command allows the status register to be written. a write enable command must previously have been executed for the device to accept the write status register command (status register bit wel must equal 1). once write enabled, the co mmand is entered by driving cs# low, sending the instruction code ?01h?, and then wr iting the status r egister data byte as illustrated in figure 8.4 . the status register bits are shown in table 6.1 on page 12 and described in section 6.4, status register on page 12 . only non-volatile status regi ster bits srp, bp3, bp2, bp1, and bp0 (bits 7, 5, 4, 3, and 2) can be written to. all other status regi ster bit locations are read-only and will no t be affected by the wr ite status register command. the cs# chip select input pin must be driven to the logic high state after the eighth bit of data has been latched in. if not, the write status r egister command is not executed. as so on as the cs# chip select input pin is driven to the logic high state, the se lf-timed write status register cycle is init iated. while the write status register cycle is in progress, the status r egister may still be r ead to check t he value of the write in progress (wip) bit. the write in progr ess (wip) bit is a 1 during the self-t imed write status register cycle, and is a 0 when it is completed. when the write status register cycle is complet ed, the write enable latch (wel) is set to a 0. the write status register command allows the block protect bits (bp3, bp2, bp1, and bp0) to be set for protecting all, a portion, or none of the memory from erase and progr am commands. protected areas become read-only (see table 7.1 on page 13 ). the write status register comma nd also allows the status register protect bit (srp) to be set. this bit is used in conjunctio n with the write protect (wp# ) pin to disable writes to the status register. when the srp bit is set to a 0 state (fac tory default) the wp# pin has no control over the status register. when the srp pin is set to a 1, the write status regi ster command is locked out while the wp# pin is low. when the wp# pin is high th e write status register command is allowed. cs# sck mode0 mode3 01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 21 20 19 18 17 16 23 22 si/io0 instruction (05h) so *=m sb status register out status register out * * high impedance 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
18 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) figure 8.4 write status register command sequence 8.5 read data (03h) the read data command allows one more data by tes to be sequentially read from the memory. the command is initiated by driving the cs# pin low and th en shifting the instruction co de ?03h? followed by a 24-bit address (a23-a0) into the si/io0 pin. the code and address bits are latched on the rising edge of the sck pin. after the address is received, the data byte of the addressed memory location will be shifted out on the so pin at the falling edge of sc k with most significant bit (msb) fi rst. the address is automatically incremented to the next higher address after each byte of da ta is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single co mmand as long as the clock continues. the command is completed by driving cs# high. the read data command sequence is shown in figure 8.5 . if a read data command is issued while an erase, program or write c ycle is in process (wip=1) the command is ignored and will not have any effects on the current cycle. the read data command allows clock rates from d.c. to a maximum of f r . see ac characteristics on page 31. figure 8.5 read data command sequence 8.6 fast read (0bh) the fast read command is similar to the read data co mmand except that it can operate at higher frequency than the traditional read data command. see ac characteristics on page 31. this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 8.6 . the dummy clocks allow the device?s internal circuits ad ditional time for setting up the initial address. during the dummy clocks the data value on the si pin is a ?don?t care?. cs# sck mode0 mode3 01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 mode3 mode0 si/io0 instruction(01h) so high impedance * *= m sb 7 6 5 4 3 2 1 0 cs# sck mode0 mode3 01 10 9 8 7 6 5 4 3 2 30 39 38 37 36 35 34 33 32 31 28 29 si/io0 instruction (03h) so high impedance 23 2 3 21 22 0 1 6 7 5 2 3 1 4 0 * * *=m sb 24-bit address data o ut 1 data o ut 2 7
august 14, 2012 S25FL204K_00_05 S25FL204K 19 data sheet (preliminary) figure 8.6 fast read command sequence 8.7 fast read dual output (3bh) the fast read dual output (3bh) command is similar to the standard fast read (0bh) command except that data is output on two pins, so and si/i o0, instead of just so. this allows data to be transferred from the S25FL204K at twice the rate of standard spi devices. the fast read dual output command is ideal for quickly downloading code from the spi flash to ram upon power-up or for applications that cache code- segments to ram for execution. similar to the fast read command, the fast read d ual output command can operate at higher frequencies than the traditional read data command. see ac characteristics on page 31. this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 8.7 . the dummy clocks allow the device's internal circuits additional time for setting up the initial add ress. the input data during the dummy clocks is ?don?t care?. however, the si/io0 pin should be hi gh-impedance prior to the fa lling edge of the first data out clock. c s # s ck 3 2 33 42 41 40 3 9 38 3 7 3 6 3 5 3 4 45 54 5 3 51 51 50 49 4 8 47 46 4 3 44 s i/io0 d u mmy clock s 6 7 5 2 3 1 4 0 * *=m s b d a t a o u t 1 7 c s # s ck mode0 mode 3 01 10 9 8 7 6 5 4 3 2 3 0 3 1 2 8 29 s i/io0 in s tr u ction (0bh) s o high imped a nce 2 3 2 3 21 22 0 1 * 24-bit addre ss 6 7 5 2 3 1 40 * 6 7 5 2 3 1 4 0 d a t a o u t 1 55 * s o
20 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) figure 8.7 fast read dual output command sequence 8.8 page program (pp) (02h) the page program command allows up to 256 bytes of data to be programmed at previously erased to all 1s (ffh) memory loca tions. a write enable command must be execut ed before the device will accept the page program command (status register bit wel must equal 1) . the command is initiated by driving the cs# pin low then shifting the command code ?02h? followed by a 24-bit address (a23-a0) and at least one data byte, into the si/io0 pin. the cs# pin must be held low fo r the entire length of the command while data is being sent to the device. the page program command sequence is shown in figure 8.8 . if an entire 256 byte page is to be programmed, the la st address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressi ng will wrap to the beginning of the page. in so me cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes with in the same page. one condition to perform a partial page program is that the number of clocks can not exceed t he remaining page length. if more than 256 bytes are sent to the device the addres sing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase commands, the cs# pin must be driven high a fter the eighth bit of the last byte has been latched. if this is not done the page program command will not be executed. after cs# is driven high, the self-timed page program command will commence for a time duration of t pp . see ac characteristics on page 31. while the page program cycle is in progress, the read status register command may still be accessed for ch ecking the status of the wip bit. the wip bi t is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other commands again. after the page program cycle ha s finished the write enabl e latch (wel) bit in t he status register is cleared to 0. the page program co mmand will not be executed if the ad dressed page is pr otected by the block protect (bp3, bp2, bp1, and bp0) bits (see table 7.1 on page 13 ). cs# sck 32 33 42 41 40 39 38 37 36 35 34 45 54 53 51 51 50 49 48 47 46 43 44 si/io0 dummy clocks so 5 7 3 5 7 3 1 1 * *=m sb 7 cs# sck mode0 mode3 01 10 9 8 7 6 5 4 3 2 30 31 28 29 si/io0 instruction (3bh) so high impedance 23 2 3 21 22 0 1 * 24-bit address 5 7 3 5 7 3 11 * 55 * 4 6 2 4 6 2 0 0 4 6 2 4 6 2 0 0 6 * * si/io0 switches from input to output data out 1 d ata out 2 d ata out 3 d ata out 4
august 14, 2012 S25FL204K_00_05 S25FL204K 21 data sheet (preliminary) figure 8.8 page program command sequence 8.9 sector erase (se) (20h) the sector erase command sets all bits in the addressed 4 kb sector to 1 (all bytes are ffh). before the sector erase command can be accepted by the device, a write enable command must be issued and decoded by the device, which sets t he write enable latch bit in the st atus register to enable any write operations. the command is initiated by driving the cs# pin low and shifting the command code ?20h? followed by a 24-bit sector a ddress (a23-a0). the sector erase command sequence is shown in figure 8.9 . the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase command will not be executed. after cs# is driven high, the self-tim ed sector erase command will commence for a time duration of t se . see ac characteristics on page 31. while the sector erase cycle is in progress, the read status regi ster command may still be accessed for checking the status of the wip bit. the wip bit is a 1 during the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other commands again. after the se ctor erase cycle has finis hed the write enable latch (wel) bit in the status r egister is cleared to 0. the sector er ase command will not be executed if the addressed page is protected by the block pr otect (bp3, bp2, bp1, and bp0) bits (see table 7.1 on page 13 ). cs# sck 40 41 50 49 48 47 46 45 44 43 41 53 2072 55 54 51 52 si/io0 data byte 2 so 6 7 5 2 3 1 40 * *=m sb data byte 256 cs# sck mode0 mode3 01 10 9 8 7 6 5 4 3 2 30 31 28 29 si/io0 instruction (02h) so high impedance 23 2 3 21 22 0 1 * 24-bit address 6 7 5 2 3 1 40 * 6 7 5 2 3 1 4 0 data byte 3 34 35 32 33 38 39 37 36 6 7 5 2 3 1 4 0 * 2078 2077 2076 2075 2074 2073 2079 mode0 mode3 * data byte 1 high impedance
22 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) figure 8.9 sector erase command sequence 8.10 block erase (be) (d8h) the block erase command sets all bits in the addressed 64 kb block to 1 (all bytes are ffh). before the be command can be accepted by the device, a write enable command must be issued and decoded by the device, which sets the write enable latch in the st atus register to enable any write operations. the command is initiated by driving the cs# pin low and shifting the command code ?d8h? followed a 24-bit block address (a23-a0). the block erase command sequence is shown in figure 8.10 . the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase command will not be executed. after cs # is driven high, the self -timed block erase command will commence for a time duration of t be . see ac characteristics on page 31. while the block erase cycle is in progress, the read status regi ster command may still be accessed for checking the status of the wip bit. the wip bit is a 1 during the block erase cycle and becomes a 0 when the cy cle is finished and the device is ready to accept other commands again. after the bl ock erase cycle has finis hed the write enable latch (wel) bit in the status r egister is cleared to 0. t he block erase command will not be executed if the addressed page is protected by the block pr otect (bp3, bp2, bp1, and bp0) bits (see table 7.1 on page 13 ). figure 8.10 block erase command sequence 8.11 chip erase (ce) (c7h) the chip erase command sets all bits to 1 (all bytes ar e ffh) inside the entire flash memory array. before the ce command can be accepted by the device, a wr ite enable command must be issued and decoded by the device, which sets the write enable latch in the st atus register to enable any write operations. the command is initiated by driving the cs# pin low and shifting the command code ?c7h?. the chip erase command sequence is shown in figure 8.11 . cs# sck mode 0 mode 3 01 31 30 29 9 8 7 6 5 4 3 2 mode3 mode0 si/io0 instruction(20h) so high impedance * *=m sb 23 22 2 1 0 24-bit address cs# sck mode 0 mode 3 01 31 30 29 9 8 7 6 5 4 3 2 mode3 mode0 si/io0 in stru ctio n (d8) so high impedance * *=m sb 23 22 2 1 0 24-bit address
august 14, 2012 S25FL204K_00_05 S25FL204K 23 data sheet (preliminary) the cs# pin must be driven high after the eighth bit has been latched. if this is not done the chip erase command will not be executed. after cs# is driven high, the self-timed chip erase command will commence for a time duration of t ce . see ac characteristics on page 31. while the chip erase cy cle is in progress, the read status register command may st ill be accessed to check the status of the wip bit. the wip bit is a 1 during the chip erase cycle and becomes a 0 when fini shed and the device is ready to accept other commands again. after the chip erase cycle has finish ed the write enable latch (wel) bit in the status register is cleared to 0. the chip erase command will not be executed if any page is protected by the block protect (bp3, bp2, bp1, and bp0) bits (see table 7.1 on page 13 ). figure 8.11 chip erase command sequence 8.12 deep power-down (dp) (b9h) the deep power-down (dp) command provides the lowe st power consumption mode of the device. it is intended for periods when the device is not in active use, and ignores all commands except for the release from deep power-down (res) command. the lowe r power consumption makes the deep power-down command especially useful for battery powered applications (see i cc1 and i cc2 in dc characteristics on page 30 .) the command is initiated by driving the cs # pin low and shifting the command code ?b9h? as shown in figure 8.12 . the cs# pin must be driven high after the eighth bit has been latched. if this is not done the deep power-down command will not be executed. after cs# is driven high, the power-down state will enter within the time duration of t dp ( see ac characteristics on page 31. ) while in the power-dow n state only the release from power-down / device id command , which restores the device to no rmal operation, will be recognized. all other commands are ignored. this includes the read status register command, wh ich is always available during normal operation. the deep po wer-down mode therefore provides the maximum data protection against unintended write operations. deep power-down mode automatically terminates when power is removed, and the device always powers up in the st andard standby mode. the device rejects any deep power-down command issued while it is executing a program, erase, or write registers operation, and continues the opera tion uninterrupted. cs# sck 05 4 3 1 2 7 6 mode0 mode0 mode3 mode3 si/io0 so high impedance instruction(c7h)
24 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) figure 8.12 deep power-down command sequence 8.13 release deep power-down / device id (abh) the release from deep power-down / device id co mmand is a multi-purpose command. the device requires the release from deep power-down command to exit th e deep power-down mode. when the device is in the deep power-down mode, all commands except releas e from deep power-down command are ignored. in addition, the abh command can also be used to read the device's 8-bit electronic device id. when used only to release the device from the power-down state, the co mmand is issued by driving the cs# pin low, shifting the command code ?abh ? and driving cs# high as shown in figure 8.13 . after the time duration of t res1 ( see ac characteristics on page 31. ) the device will resume normal operation and other commands will be accepted. the cs# pi n must remain high during the t res1 time duration. when used only to obtain the device id while not in the deep power-dow n state, the command is initiated by driving the cs# pin low and shifting the command code ? abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falli ng edge of sck with most significa nt bit (msb) first as shown in figure 8.14 . the device id value for the S25FL204K is listed in manuf acturer and device identifi cation table. the device id can be read continuously. the command is completed by driving cs# high. when used to release the device from the deep power- down state and obtain the device id, the command is the same as previously described, and shown in figure 8.14 , except that after cs# is driven high it must remain high for a time duration of t res2 ( see ac characteristics on page 31. ). after this time duration the device will resume normal operation and other commands will be accepted. if the release from deep power- down / device id command is issued while an erase, pr ogram or write cycle is in process (when wip equals 1) the command is ignore d and will not have any effe cts on the current cycle. figure 8.13 release deep power-down command cs# sck 05 4 3 1 2 7 6 mode0 mode3 si/io0 so high impedance instruction(b9h) mode3 t dp standard current power-down current mode0 cs# sck 05 4 3 1 2 7 6 mode0 mode3 si/io0 so high impedance instruction(abh) mode3 t res1 deep power-down current high performance current stand-by current mode0
august 14, 2012 S25FL204K_00_05 S25FL204K 25 data sheet (preliminary) figure 8.14 release deep power-down / device id command sequence 8.14 read manufacturer / device id (90h) the read manufacturer/device id command is an alternative to the release from deep power-down /device id command that provides both the jedec assi gned manufacturer id and the specific device id. the read manufacturer/device id command is very si milar to the release from deep power-down / device id command. the command is initiated by driving the cs# pin low and shifting the command code ?90h? followed by a 24-bit address (a23-a0) of 000000h. afte r which, the manufacturer id for spansion (01h) and the device id are shifted out on t he falling edge of sck with most signifi cant bit (msb) first as shown in figure 8.15 . the device id values for the S25FL204K are listed in table 8.2 on page 15 . if the 24-bit address is initially set to 000001h the device id will be read first, followed by the manufacturer id. *=m sb cs# sck mode0 mode3 01 10 9 8 7 6 5 4 3 2 30 31 28 29 si/io0 instruction (abh ) so high impedance 23 2 3 21 22 0 1 * 3 dummy bytes 34 35 32 33 38 37 36 6 7 5 2 3 1 4 0 * mode3 mode0 device id ** t res2 power down current high performance mode current stand-by current
26 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) figure 8.15 read manufacturer / device id command sequence 8.15 read identification (rdid) (9fh) for compatibility reasons, the S25FL204K provides seve ral commands to electronica lly determine the identity of the device. the read jedec id command is compat ible with the jedec standard for spi compatible serial memories that was adopted in 2003. the command is initiated by driving the cs# pin low and shifting the command code ?9fh?. the jedec assigned manufacturer id byte for spansion (01h) and two device id bytes, memory type (id15-id8) and capacity (id7-id0) are then shifted out on the falling e dge of sck with most signifi cant bit (msb) first as shown in figure 8.16 . for memory type and capacity values refer to table 8.2, manufacturer and device identification on page 15 . c s # s ck 3 2 33 42 41 40 3 9 38 3 7 3 6 3 5 3 4 45 46 4 3 44 s i/io0 62 *=m s b c s # s ck mode0 mode 3 01 10 9 8 7 6 5 4 3 2 3 0 3 1 2 8 29 s i/io0 in s tr u ction (90h) s o high imped a nce 2 3 2 3 21 22 0 1 * addre ss ? 000000 h ? 6 7 5 2 3 1 40 * * m a n u f a ct u rer id device id** mode0 mode 3
august 14, 2012 S25FL204K_00_05 S25FL204K 27 data sheet (preliminary) figure 8.16 read jedec id command sequence cs# sck mode0 mode3 01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 si/io0 instruction (9fh) so manufacturer id * high impedance cs# sck 16 17 31 30 29 28 27 26 25 24 23 22 21 20 19 18 mode3 mode0 si/io0 memory type id 15-id8 so * *=m sb 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 capacity id7-id0 *
28 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) 9. electrical specifications 9.1 power-up timing figure 9.1 power-up timing notes: 1. the parameters are characterized only. 2. v cc (max.) is 3.6v and v cc (min.) is 2.7v. table 9.1 power-up voltage and timing parameter symbol type unit min max v cc (min) to cs# low t vsl (1) 10 s time delay before write instruction t puw (1) 110ms write inhibit threshold voltage v wi (1) 12v vcc (max) vcc (min) v wi reset stast t vsl cs# must track vcc program, e rase, and write instruction are ignored read instructions allowed device is fully accessible t puw vcc time
august 14, 2012 S25FL204K_00_05 S25FL204K 29 data sheet (preliminary) 9.2 absolute maximum ratings stresses above the values so mentioned above may cause permanent damage to the device. these values are for a stress rating only and do not imply that t he device should be operated at co nditions up to or above these values. notes: 1. specification for S25FL204K is advance information. see advance information designation at the beginning of this document. 2. this device has been designed and tested for the specified operation ranges. proper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may affect device reliability. exposure beyond absolute maximum rati ngs may cause permanen t damage. 3. compliant with jedec standard j-std-20c for small body sn-p b or pb-free (green) assembly and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 9.3 recommended operating ranges note: 1. recommended operating ranges define those limits between which the functionality of the device is guaranteed. table 9.2 absolute maximum ratings parameters symbol conditions range unit supply voltage v cc -0.6 to +4.0 v voltage applied on any pin v io relative to ground -0.6 to v cc +0.4 v transient voltage on any pin v iot <20 ns transient relative to ground -2.0 to v cc +2.0 v storage temperature t stg -65 to +150 c lead temperature t lead (note 3) c table 9.3 recommended operating ranges parameter symbol conditions spec unit min max supply voltage v cc f r = 85 mhz, f r = 44 mhz 2.7 3.6 v ambient temperature, operating t a industrial -40 +85 c
30 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) 9.4 dc characteristics this section summarizes the dc characteristics of t he device. designers should check that the operating conditions in their circuit match the measurement condi tions specified in the ac measurement conditions in table 9.6 on page 31 , when relying on the quoted parameters. notes: 1. tested on sample basis and specified through design and characterization data. t a =25c, v cc 3v. 2. checker board pattern. 9.5 ac measurement conditions table 9.4 dc characteristics symbol (notes) parameter (notes) conditions (notes) spec unit min typ max c in (1) input capacitance v in = 0v (2) 6pf c out (1) output capacitance v out = 0v (2) 8pf i li input leakage 2 a i lo i/o leakage 2 a i cc1 standby current cs# = v cc , v in = gnd or v cc 15 35 a i cc2 power-down current cs# = v cc , v in = gnd or v cc 15 32 a i cc3 current read data / dual output read 33 mhz (2) c = 0.1 v cc / 0.9 v cc do = open 10/12 15/18 ma i cc3 current read data / dual output read 100 mhz (2) c = 0.1 v cc / 0.9 v cc so = open 25 ma i cc4 current page program cs# = v cc 15 20 ma i cc5 current write status register cs# = v cc 10 18 ma i cc6 current sector/block erase cs# = v cc 20 25 ma i cc7 current chip erase cs# = v cc 20 25 ma v il input low voltage -0.5 vcc x 0.3 v v ih input high voltage v cc x0.7 v cc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = -100 a v cc -0.2 v table 9.5 ac measurement conditions symbol parameter min max unit c l load capacitance 30 pf t r , t f input rise and fall times 5 ns v in input pulse voltages 0.2 v cc to 0.8 v cc v vtin input timing reference voltages 0.3 v cc to 0.7 v cc v vton output timing reference voltages 0.5 v cc to 0.5 v cc v
august 14, 2012 S25FL204K_00_05 S25FL204K 31 data sheet (preliminary) figure 9.2 ac measurement i/o waveform 9.6 ac characteristics inp u t level s 0. 8 vcc 0.2 vcc 0. 3 vcc 0.7 vcc inp u t a nd o u tp u t timing reference level s table 9.6 ac characteristics (sheet 1 of 2) symbol (notes) alt parameter (notes) spec unit min typ max f r f c clock frequency for all instructions, except read data (03h) and dual output (3bh) d.c. 85 mhz clock frequency for dual output (3bh) 85 mhz f r clock freq. read data instruction (03h) d.c. 44 mhz t clh , t cll (1) clock high, low time for all instructions except read data (03h) 4ns t crlh , t crll (1) clock high, low time for read data (03h) instruction 4ns t clch (2) clock rise time peak to peak 0.1 v/ns t chcl (2) clock fall time peak to peak 0.1 v/ns t slch t css cs# active setup time relative to sck 6 ns t chsl cs# not active hold time relative to sck 5 ns t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 5 ns t chsh cs# active hold time relative to sck 5 ns t shch cs# not active setup time relative to sck 5 ns t shsl t csh cs# deselect time (for array read 'array read / erase or program ' read status register) 50/100 ns t shqz (2) t dis output disable time 6 ns t clqv t v clock low to output valid 10 ns t clqx t ho output hold time 0 ns t hlch hold# active setup time relative to sck 5 ns t chhh hold# active hold time relative to sck 5 ns t hhch hold# not active setup time relative to sck 5 ns t chhl hold# not active hold time relative to sck 5 ns t hhqx (2) t lz hold# to output low-z 7 ns t hlqz (2) t hz hold# to output high-z 12 ns t whsl (3) write protect setup time before cs# low 20 ns t shwl (3) write protect hold time after cs# high 100 ns t dp (2) cs# high to power-down mode 3 s t res1 (2) cs# high to standby mode without electronic signature read 3s t res2 (2) cs# high to standby mode with electronic signature read 1.8 s t w write status register time 10 15 ms
32 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and/or characterization, not 100% tested in production. 3. only applicable as a constraint for a write status register instruction when sector protect bit is set to 1. 4. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes programmed. 5. max value shown is for less than 10k cycles. for greater than 10k cycles, max value is 5.3s. 6. max value shown is for less than 10k cycles. for greater than 10k cycles, max value is 8.4s. figure 9.3 serial output timing figure 9.4 input timing t bp1 byte program time (first byte) (4) 30 50 s t bp2 additional byte program time (after first byte) (4) 612s t pp page program time 1.5 5 ms t se sector erase time (4 kb) 50 300 ms t be (5) block erase time (64 kb) 0.5 2 s t ce (6) chip erase time 3.5 7 s table 9.6 ac characteristics (sheet 2 of 2) symbol (notes) alt parameter (notes) spec unit min typ max c s # s ck s o / s i(io0) (note) l s b o u t t clqx t clqv t clqx t clqv t cl t ch t clql t clqh t s hqz note: s i(io0) i s a n o u tp u t o nly for the f as t re a d d ua l o u tp u t comm a nd ( 3 bh) c s # s ck t ch s l t s lch t clch t s h s l t s hch t ch s h t chcl s i/io0 t dvch t chdx m s b in l s b in s o high imped a nce
august 14, 2012 S25FL204K_00_05 S25FL204K 33 data sheet (preliminary) figure 9.5 hold timing cs# sck si/io0 t hlqz t chhl so t hlch hold# thhch t h h q h t chhh
34 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) 10. package material 10.1 8-pin soic 150-mil package (soa 008) g1019 \ 16-038.3f \ 10.06.11 notes: 1. all dimensions are in both inches and millmeters. 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. d and e1 dimensions are determined at datum h. 4. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outmost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash. but including any mismatch between the top and bottom of the plastic body. 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified package length. 7. the dimensions apply to the flat section of the lead between 0.10 to 0.25 mm from the lead tip. 8. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.10 mm total in excess of the "b" dimension at maximum material condition. the dambar cannot be located on the lower radius of the lead foot. 9. this chamfer feature is optional. if it is not present, then a pin 1 identifier must be located within the index area indicated. 10. lead coplanarity shall be within 0.10 mm as measured from the seating plane.
august 14, 2012 S25FL204K_00_05 S25FL204K 35 data sheet (preliminary) 10.2 8-pin soic 208-mil package (soc 008) 3 602 \ 16-0 38 .0 3 \ 9.1.6 note s : 1. all dimen s ion s are in both inche s and millmeter s . 2. dimen s ioning and tolerancing per a s me y14.5m - 1994. 3 . dimen s ion d doe s not include mold fla s h, protru s ion s or gate burr s . mold fla s h, protru s ion s or gate burr s s hall not exceed 0.15 mm per end. dimen s ion e1 doe s not include interlead fla s h or protru s ion interlead fla s h or protru s ion s hall not exceed 0.25 mm per s ide. d and e1 dimen s ion s are determined at datum h. 4. the package top may be s maller than the package bottom. dimen s ion s d and e1 are determined at the outmo s t extreme s of the pla s tic body exclu s ive of mold fla s h, tie bar burr s , gate burr s and interlead fla s h. but including any mi s match between the top and bottom of the pla s tic body. 5. datum s a and b to be determined at datum h. 6. "n" i s the maximum number of terminal po s ition s for the s pecified package length. 7. the dimen s ion s apply to the flat s ection of the lead between 0.10 to 0.25 mm from the lead tip. 8 . dimen s ion " b " doe s not include dambar protru s ion. allowable dambar protru s ion s hall be 0.10 mm total in exce ss of the " b " dimen s ion at maximum material condition. the dambar cannot be located on the lower radiu s of the lead foot. 9. thi s chamfer feature i s optional. if it i s not pre s ent, then a pin 1 identifier mu s t be located within the index area indicated. 10. lead coplanarity s hall be within 0.10 mm a s mea s ured from the s eating plane. package s oc 00 8 (inche s ) s oc 00 8 (mm) jedec s ymbol min max min max a 0.069 0.0 8 5 1.75 3 2.159 a1 0.002 0.009 8 0.051 0.249 a2 0.067 0.075 1.70 1.91 b 0.014 0.019 0. 3 56 0.4 83 b 10.01 3 0.01 8 0. 33 0 0.457 c 0.0075 0.0095 0.191 0.241 c1 0.006 0.00 8 0.152 0.20 3 d 0.20 8 b s c 5.2 83 b s c e 0. 3 15 b s c 8 .001 b s c e1 0.20 8 b s c 5.2 83 b s c e .050 b s c 1.27 b s c l 0.020 0.0 3 0 0.50 8 0.762 l1 .049 ref 1.25 ref l2 .010 b s c 0.25 b s c n 8 8 0? 8 ?0? 8 ? 1 5? 15? 5? 15? 2 0? 0?
36 S25FL204K S25FL204K_00_05 august 14, 2012 data sheet (preliminary) 11. revision history section description revision 01 (november 2, 2011) initial release revision 02 (december 21, 2011) dc characteristics updated i cc2 values revision 03 (january 6, 2012) distinctive features updated standby current value revision 04 (june 8, 2012) global changed data sheet designation to ?preliminary? changed f r to 86 mhz recommended operating ranges table changed supply voltage frequency dc characteristics table updated i cc1 and i cc2 values ac characteristics table modified f r , f r , and t clqv revision 05 (august 14, 2012) status register changed status register bit r0 from ?busy? to ?wip? global changed ?busy? to ?wip? ac characteristics ac characteristics table: changed f r max value from 86 to 85 changed t slch min value from 5 to 6 added note 5 and note 6
august 14, 2012 S25FL204K_00_05 S25FL204K 37 data sheet (preliminary) colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any ot her warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2011-2012 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse?, ornand? and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. other names used are for informational purposes only and may be trademarks of their respective owners.

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